Job Description

**Position:** FPGA Design Engineer **Job Description:** Principal Accountabilities * RTL development for ASIC / FPGA * Responsible for completion of front end design flow (spec to RTL / Netlist) * **Annual Hiring Range/Hourly Rate:** $92,200.00 - $203,500.00 Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer. **Location:** US-CA-San Jose, California (eInfochips) **Time Type:** Full time **Job Category:** Engineering Services **EEO Statement:** Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) ( _We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application._ _In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information._ Arrow Electronics, Inc.'s policy is to provide equal employment opportunities to all qualified employees and applicants without regard to race, color, religion, age, sex, marital status, gender identity or expression, sexual orientation, national origin, disability, citizenship, veran status, genetic information, or any other characteristics protected by applicable state, federal or local laws. Our policy of equal employment opportunity and affirmative action applies to all employment decisions personnel policies and practices, or programs.

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Hourly pay, Full time, Work experience placement, Local area,

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